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SRAMs)"]}),h.jsx(ce,{years:"Independent Project/ Study",studentData:["Class of 2021","Lakshay Kumar Shringey (ADCs for In-Memory-Compute) ","Gaurav Srivastav ( Analog - Current based In Memory Computation )","Divya Sareen (Simulink Model OF IMC array (post decoder) )","Mohammad Tabish Qumar (Analog BL current mode Compute in Memory)","N Kartheek Ram Reddy (Design of Bit Serial Architecture for In-Memory Compute)","Shubham Goyal (Non-Linearity Management)","Md Adil Arif (Design of Razor flip flop for speculative computing) ","Ranjith Srinivas A B (Implementation of In memory multiplication using Bit serial architecture) ","Pulkita Gupta (Non-Linearity Management in IMC)","Abhinav Bajoria (Non-Linearity Management in IMC)","Class of 2020","Robinson Devasia (Hardware Accelerators for Convolutional Neural Networks)","Sapna Sharma (Different Technologies for In-Memory Computing)","Aditya Khandelwal (Functional Safety For Automotive Applications: Safety Mechanisms in Digital Design)","Jitendra Yadav (Bit-Serial architectures for In-Memory Computation)","Shuchi Nagaria (Energy Efficient Charge Pumps in NVM) ","Shivani Mamodia (Use of ML techniques in Silicon Validation) ","Shaikh Tauseef Hasan (IEEE 1149.1 JTAG Protocol)","Surabhi Rukmangad (Machine Learning in Silicon Validation) ","Ayesha Yadav (Level Shifters for Memory Design) ","Spoorthy Nagaraja (Functional Safety For Automotive Applications: ISO26262 ASIL Requirements)","Aman Vyas (Different Layout Topologies of a Balanced Sense Amplifier)","Bandana Prasad (Multilevel Wordline Driver for SRAMs)","Shaikh Tauseef Hasan (Radiation Hardened Flip Flop)","Srashti Doser (Impact of Limiting Drive Strengths in a library on PPA of a module)","Shivam Agarwal (Emerging Memories: MRAMs)","Neerupama Gupta (Emerging Memories: FRAMs","Shashank Neeraj Dwivedi (Process Variations Monitoring Circuits)","Ashish Seth (On-Chip Characterization of Memory)","Shaikh Tauseef Hasan (Radiation Hardened Flip Flops)","Priyanka Kandpal (SRAM DRV Estimation Techniques)","Feraj Husain (Transition Faults in SRAMs - Cause, Effect, and Diagnosis)","Shubhesh Tatwadarshi (Verification of Multi-bit Accelerator)","Aakash Tyagi (Design Failure Mode and Effect Analysis of Memory Architecture)","Aanchal Kumari (Multi-bit Flip Flop)","Devayanshu Mittal (Different Archtectures for On-Chip Computing and Storage)","Vaibhav Verma (A Survey of Single-Ended Sense Amplifiers)","Aparna Mishra (A Survey of Read and Write Assist Schemes in SRAMs)","Srashti Doser (Figures of Merit of On-chip Temprature Sensor)","Kamakshi Pandey (Comparison of Radiation Hardened Flip Flops)","Aman Vyas (Inductorless DC-DC Low Power Voltage Regulators)","Class of 2019","Avinash Pandit (Low Power Wide Tuning Range Voltage Controlled Oscillator)","Ishan Bhatia (ASIL standards for Automotive Safety- a Memory Design Perspective)","Ishit Agarwal (Different layouts of Voltage Latch Sense Amplifier - Impact of Structural Matching)","Mishal Kumar (Canary and Razor Circuits in SRAMs)","Shivendra Singh (Memory Defect Detection Based on ASIL Documentation)","Naina Aggarwal (Impact of Supply Noise on Retention Modes in Memory)","Swastika Kumari (To Explore and Evaluate Modifications in System Architecture for Including Razor SRAMs in High Performance and Low Power SoCs)","Pendharkar Abhijeet Ramesh (Making Circuits Attack Proof)","Sakshar Pathak (Low Power Low Drop Out (LDO) Regulators)","Feraj Husain (Transition Faults in SRAM: Cause, Effect and Diagnosis)"]})]})]});function ay(){return h.jsxs("div",{style:{textAlign:"center",marginTop:"120px"},children:[h.jsx(lt,{imagesGrp:["./2.jpg","./19.jpg","./23.jpg","./14.jpg","./4.jpg","./20.jpg","./5.jpg","./6.jpg","./21.jpg","./10.jpg","./22.jpg","./11.jpg","./17.jpg","./18.jpg"]}),h.jsx(ce,{years:"2024",studentData:["A. Shroti and A. Grover, “Design Of High-Density Iso-Stable Asymmetric Memory Cell With Upto 10X Reduced Leakage,” in 2024 IEEE International Symposium on Circuits and Systems (ISCAS), IEEE, 2024, pp. 1–5. Accessed: Aug. 03, 2024. [Online]. Available: https://ieeexplore.ieee.org/abstract/document/10558626/","N. Chawla, G. Desoli, A. Grover, T. Boesch, S. P. Singh, and M. Ayodhyawasi, “Tagged memory operated at lower vmin in error tolerant system.” Google Patents, Feb. 08, 2024. Accessed: Aug. 03, 2024. [Online]. Available: https://patents.google.com/patent/US20240045589A1/en"]}),h.jsx(ce,{years:"2023",studentData:["B. Iqbal, A. Grover, and H. Rawat, “A Common Mode Insensitive Process Tolerant Sense Amplifier Design for In Memory Compute Applications in 65nm LSTP Technology,” in 2023 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems (VLSID), IEEE, 2023, pp. 121–126. Accessed: Aug. 03, 2024. [Online]. Available: https://ieeexplore.ieee.org/abstract/document/10089940/","D. Batabyal, S. K. Singh, R. K. Mishra, and A. Grover, “A sense amplifier based bulk built-in current sensor for detecting laser-induced currents,” in 2023 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems (VLSID), IEEE, 2023, pp. 69–74. Accessed: Aug. 03, 2024. [Online]. Available: https://ieeexplore.ieee.org/abstract/document/10089947/","N. Chawla, A. Grover, G. Desoli, K. J. Dhori, T. Boesch, and P. Kumar, “Computing system power management device, system and method.” Google Patents, Aug. 15, 2023. Accessed: Aug. 03, 2024. [Online]. Available: https://patents.google.com/patent/US11726543B2/en","N. Chawla, A. Grover, G. Desoli, K. J. Dhori, T. Boesch, and P. Kumar, “Computing system power management device, system and method.” Google Patents, Nov. 02, 2023. Accessed: Aug. 03, 2024. [Online]. Available: https://patents.google.com/patent/US20230350483A1/en","S. Marwah, S. K. Dubey, and A. Grover, “Design and evaluating performance of hardware accelerators for implementation of neural networks,” 2023, Accessed: Aug. 03, 2024. [Online]. Available: https://repository.iiitd.edu.in/jspui/handle/123456789/1543","A. Gupta, A. Grover, and J. Sharma, “Design thinking for social innovation: the tale of humankind,” 2023, Accessed: Aug. 03, 2024. [Online]. Available: https://repository.iiitd.edu.in/jspui/handle/123456789/1624","N. Chawla, T. Roy, A. Grover, and G. Desoli, “Elements for in-memory compute.” Google Patents, Nov. 28, 2023. Accessed: Aug. 03, 2024. [Online]. Available: https://patents.google.com/patent/US11829730B2/en","A. Mishra and A. Grover, “Groovega private label,” 2023, Accessed: Aug. 03, 2024. [Online]. Available: https://repository.iiitd.edu.in/xmlui/handle/123456789/1485","A. Ranjan and A. Grover, “Hardware chacha,” 2023, Accessed: Aug. 03, 2024. [Online]. Available: https://repository.iiitd.edu.in/jspui/handle/123456789/1458","A. Rana and A. Grover, “Helping people to acquire interpersonal skills,” 2023, Accessed: Aug. 03, 2024. [Online]. Available: https://repository.iiitd.edu.in/jspui/handle/123456789/1610","R. Jaiswal and A. Grover, “Helping startups attract more clients using personalized outreach strategy,” 2023, Accessed: Aug. 03, 2024. [Online]. Available: https://repository.iiitd.edu.in/xmlui/handle/123456789/1529","A. Grover and T. Roy, “High density array, in memory computing.” Google Patents, Oct. 24, 2023. Accessed: Aug. 03, 2024. [Online]. Available: https://patents.google.com/patent/US11798615B2/en","A. Grover, T. Roy, and N. Chawla, “In-memory compute array with integrated bias elements.” Google Patents, Mar. 14, 2023. Accessed: Aug. 03, 2024. [Online]. Available: https://patents.google.com/patent/US11605424B2/en","A. Grover, T. Roy, and N. Chawla, “In-memory compute array with integrated bias elements.” Google Patents, Jun. 15, 2023. Accessed: Aug. 03, 2024. [Online]. Available: https://patents.google.com/patent/US20230186983A1/en","T. Roy and A. Grover, “Memory calibration device, system and method.” Google Patents, Oct. 03, 2023. Accessed: Aug. 03, 2024. [Online]. Available: https://patents.google.com/patent/US11776650B2/en","N. Chawla, T. Roy, and A. Grover, “Memory management device, system and method.” Google Patents, Sep. 05, 2023. Accessed: Aug. 03, 2024. [Online]. Available: https://patents.google.com/patent/US11749343B2/en","N. Chawla, T. Boesch, A. Grover, S. P. Singh, and G. Desoli, “Streaming access memory device, system and method.” Google Patents, Nov. 21, 2023. Accessed: Aug. 03, 2024. [Online]. Available: https://patents.google.com/patent/US11823771B2/en","N. Chawla, G. Desoli, A. Grover, T. Boesch, S. P. Singh, and M. Ayodhyawasi, “Tagged memory operated at lower vmin in error tolerant system.” Google Patents, Dec. 05, 2023. Accessed: Aug. 03, 2024. [Online]. Available: https://patents.google.com/patent/US11836346B2/en","S. Gupta and A. Grover, “Tuvoi (toy consignment service),” 2023, Accessed: Aug. 03, 2024. [Online]. Available: https://repository.iiitd.edu.in/xmlui/handle/123456789/1573","V. Vardhan and A. Grover, “Video and advertisement production company,” 2023, Accessed: Aug. 03, 2024. [Online]. Available: https://repository.iiitd.edu.in/jspui/handle/123456789/1618"]}),h.jsx(ce,{years:"2022",studentData:["M. K. Srivastav, R. Mishra, A. Grover, K. J. Dhori, and H. Rawat, “3-Stage Pipelined Hierarchical SRAMs with Burst Mode Read in 65nm LSTP CMOS,” in 2022 IEEE International Symposium on Circuits and Systems (ISCAS), IEEE, 2022, pp. 1546–1550. Accessed: Aug. 03, 2024. [Online]. Available: https://ieeexplore.ieee.org/abstract/document/9937582/","B. Iqbal, A. Grover, and H. Rawat, “A process and data variations tolerant capacitive coupled 10T1C sram for in-memory compute (IMC) in deep neural network accelerators,” in 2022 IEEE 4th International Conference on Artificial Intelligence Circuits and Systems (AICAS), IEEE, 2022, pp. 459–462. Accessed: Aug. 03, 2024. [Online]. Available: https://ieeexplore.ieee.org/abstract/document/9870026/","N. Chawla, T. Roy, A. Grover, and G. Desoli, “Elements for in-memory compute.” Google Patents, Oct. 18, 2022. Accessed: Aug. 03, 2024. [Online]. Available: https://patents.google.com/patent/US11474788B2/en","A. Grover and T. Roy, “High-density array, in memory computing.” Google Patents, May 17, 2022. Accessed: Aug. 03, 2024. [Online]. Available: https://patents.google.com/patent/US11335397B2/en","T. Roy and A. Grover, “Memory calibration device, system and method.” Google Patents, Jul. 26, 2022. Accessed: Aug. 03, 2024. [Online]. Available: https://patents.google.com/patent/US11398289B2/en","N. Chawla, T. Roy, and A. Grover, “Memory management device, system and method.” Google Patents, Feb. 22, 2022. Accessed: Aug. 03, 2024. [Online]. Available: https://patents.google.com/patent/US11257543B2/en","A. Mohd and A. Grover, “Power estimation of in-memory compute based memory arrays using simulink blocks,” PhD Thesis, IIIT-Delhi, 2022. Accessed: Aug. 03, 2024. [Online]. Available: https://repository.iiitd.edu.in/xmlui/handle/123456789/1324","C. Kumar, R. Kumar, A. Grover, S. Chatterjee, K. J. Dhori, and H. Rawat, “Retention Problem Free High Density 4T SRAM cell with Adaptive Body Bias in 18nm FD-SOI,” in 2022 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems (VLSID), IEEE, 2022, pp. 228–233. Accessed: Aug. 03, 2024. [Online]. Available: https://ieeexplore.ieee.org/abstract/document/9885984/","N. Chawla, G. Desoli, A. Grover, T. Boesch, S. P. Singh, and M. Ayodhyawasi, “Tagged memory operated at lower vmin in error tolerant system.” Google Patents, Jun. 14, 2022. Accessed: Aug. 03, 2024. [Online]. Available: https://patents.google.com/patent/US11360667B2/en","S. Vasudev, K. Kartickraj, and A. Grover, “Up to 13.7% Increase in Throughput of RISC V SoC Using Timing Speculative Razor SRAM,” in 2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), IEEE, 2022, pp. 222–225. Accessed: Aug. 03, 2024. [Online]. Available: https://ieeexplore.ieee.org/abstract/document/10090381/"," B. Iqbal, A. Bajoria, P. Gupta, S. Goyal, and A. Grover, “Word Line Underdrive Technique to Increase Signal Swing and Linearity for In-Memory Compute Applications (IMC) in 65nm LSTP technology,” in 2022 IEEE 19th India Council International Conference (INDICON), IEEE, 2022, pp. 1–6. Accessed: Aug. 03, 2024. [Online]. Available: https://ieeexplore.ieee.org/abstract/document/10039745/"]}),h.jsx(ce,{years:"2021",studentData:["S. Bansal and A. Grover, “Process Compensated Diagnostic Circuit For Impending Fault Detection In SRAM Write Drivers,” in 2021 IEEE Asia Pacific Conference on Circuit and Systems (APCCAS), IEEE, 2021, pp. 185–188. Accessed: Aug. 03, 2024. [Online]. Available: https://ieeexplore.ieee.org/abstract/document/9687764/","A. Grover, T. Roy, and N. Chawla, “In-memory compute array with integrated bias elements,” US11094376B2, Aug. 17, 2021 Accessed: Aug. 03, 2024. [Online]. Available: https://patents.google.com/patent/US11094376B2/en","A. Saxena et al., “Design Of High Density Memory Cell Library For Low Voltage Operation In 65nm LSTP Technology,” in 2021 IEEE 18th India Council International Conference (INDICON), IEEE, 2021, pp. 1–7. Accessed: Aug. 03, 2024. [Online]. Available: https://ieeexplore.ieee.org/abstract/document/9691642/","M. K. Srivastav et al., “Charge scavenging gate coupled hierarchical bitline scheme for ultra-low power srams in 65nm lstp cmos,” in 2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS), IEEE, 2021, pp. 1–6. Accessed: Aug. 03, 2024. [Online]. Available: https://ieeexplore.ieee.org/abstract/document/9665552/","M. Aamir, S. Sharma, and A. Grover, “ChaCha20-in-Memory for Side-Channel Resistance in IoT Edge-Node Devices,” IEEE Open J. Circuits Syst., vol. 2, pp. 833–842, 2021.","S. Kar and A. Grover, “A 585mV, 16.6 fJ/cycle, 0.2 μW Variation Tolerant Scannable Hybrid Flip-Flop in 65nm CMOS LSTP,” in 2021 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia), IEEE, 2021, pp. 1–4. Accessed: Aug. 03, 2024. [Online]. Available: https://ieeexplore.ieee.org/abstract/document/9701453/","K. Anjali, S. Saha, A. Grover, Reduced March iC- Test for Detecting Ageing Induced Faults in Memory Address Decoders (Accepted in VLSID 2021)","F. Husain, B. Iqbal, A. Grover, A 0.4uA Offset, 6ns Sensing-time Multi-level Sense Amplifier for Resistive Non-Volatile Memories in 65nm LSTP Technology (Accepted in VLSID 2021) "]}),h.jsx(ce,{years:"2020",studentData:['P. Shukla, P. Singh, T. Maheshwari, A. Grover, V. Rana, "A 800MHz, 0.21pJ, 1.2V to 6V Level Shifter Using Thin Gate Oxide Devices in 65nm LSTP" 2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2020','K. Pandey, A. Grover, A. Jain, "Methodology to Estimate Robustness of Layouts of Radiation Hardened Flip-Flops to High Energy Radiations", 2020 IEEE 17th India Council International Conference (INDICON), 2020','B. Iqbal, M. Arij, T. Bansal, A. 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Gupta, “A 0.47V-1.17V 32KB Timing Speculative SRAM in 28nm HKMG CMOS”, 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020","S. N. Dwivedi, A. K. Seth, A. Grover, “Design & Benchmark of Single Bit & Multi Bit Sequential Elements in 65nm for Low Standby Power Consumption”, 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020","V. Verma, F. Akhtar, A. Grover, “Comparative Analysis and Implementation of Single-ended Sense Amplifier Schemes using 65nm LSTP CMOS Technology”, 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020","S. Singh, V. Gupta, A. Grover, K. J. Dhori, “Diagnostic Circuit for Latent Fault Detection in SRAM Row Decoder”, 2020 21st International Symposium on Quality Electronic Design (ISQED), 2020, pp. 395-400","V. Patil, A. Grover, A. Parashar, “Design of Sense Amplifier for Wide Voltage range Operation of Split Supply Memories in 22nm HKMG CMOS Technology”, 2020 33rd International Conference on VLSI Design and 2020 19th International Conference on Embedded Systems (VLSID), 2020, pp. 37-42"]}),h.jsx(ce,{years:"2019",studentData:["V. Gupta, S. Kapur, S. Saurabh, A. Grover, “Resistive Random Access Memory: A Review of Device Challenges”, IETE Technical Review, 2019"]}),h.jsx(ce,{years:"2018",studentData:["A. Mamgain, A. Grover, “A 81nW Error Amplifier Design for Ultra Low Leakage Retention Mode Operation of 4Mb SRAM Array in 40nm LSTP Technology”, Proceedings of IEEE International System-on-Chip Conference (SOCC) 2018 "]}),h.jsx(ce,{years:"2017",studentData:["S. Pathak, A. Grover, M. Pohit, N. Bansal, “LoCCo-Based Scan Chain Stitching for Low Power DFT”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol 25, Issue 11, pp 3227-3236, 2017","A. Grover, G.S. Visweswaran, C. Parthasarathy, M. Daud, D. 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Grover, "An effective test methodology enabling detection of weak bits in SRAMs: Case study in 28nm FDSOI," 2016 20th International Symposium on VLSI Design and Test (VDAT), 2016 ','A. Ganguly, S. Goyal, S. Bhatia and A. Grover, "New stable loadless 6T dual-port SRAM cell design," 2016 20th International Symposium on VLSI Design and Test (VDAT), 2016 ']}),h.jsx(ce,{years:"2015 & EARLIER",studentData:['A. Grover, G. S. Visweswaran, C. R. Parthasarathy, M. Daud, G. Moritz, J.-P. Noel, B. Giraud, D. Turgis and P. Kumar, "Low Standby Power Capacitively Coupled Sense Amplifier for Wide Voltage Range Operation of Dual Rail SRAMs," Proceedings of IEEE International Conference on IC Design and Technology (ICICDT), 2015','G. Narang, A. Fell, P. R. Gupta and A. Grover, "Floorplan and congestion aware framework for optimal SRAM selection for memory subsystems," 2015 28th IEEE International System-on-Chip Conference (SOCC), 2015 ','G. Narang, P. Sharma, M. Jain and A. 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Grover, "Comparative analysis of SRAM cells in sub-threshold region in 65nm," International Conference on Advances in Computer Engineering and Applications, 2015 ','E. Beigné, A. Valentian, I. Miro-Panades ; R. Wilson ; P. Flatresse ; F. Abouzeid ; T. Benoist ; C. Bernard ; S. Bernard ; O. Billoint ; S. Clerc ; B. Giraud ; A. Grover ; J. L. Coz ; J.-P. Noel ; O. Thomas ; Y. Thonnart , "A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits VLIW DSP Embedding F MAX Tracking," in IEEE Journal of Solid-State Circuits, vol. 50, no. 1, pp. 125-136, Jan. 2015 ','R. Wilson, E. Beigne, P. Flatresse, A. Valentian, F. Abouzeid, T. Benoist, C. Bernard, S. Bernard, O. Billoint, S. Clerc, B. Giraud, A. Grover, J. L. Coz, I. M. Panadez, J.-P. Noel, B. Pelloux-Prayer, P. Roche, O. Thomas, Y. Thonnart, D. Turgis, F. Clermidy and P. Magarshack, "A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP Embedding Fmax Tracking," Proceedings of IEEE International Solid State Circuits Conference (ISSCC), 2014','E. Beigne, A. Valentian, B. Giraud, O. Thomas, T. Benoist, Y. Thonnart, S. Bernard, G. Moritz, O. Billoint, Y. Maneglia, P. Flatresse, J.-P. Noel, F. Abouzeid, B. PellouxPrayer, A. Grover, S. Clerc, P. Roche, J. Le Coz, S. Engels and R. Wilson, "Ultra-Wide Voltage Range designs in Fully-Depleted Silicon-On-Insulator FETs", Proceedings of IEEE Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013','G. Moritz, B. Giraud, J.-P. Noel, D. Turgis and A. Grover, "Optimization of a Voltage Sense Amplifier Operating in Ultra Wide Voltage Range with Back Bias Design Techniques in 28nm UTBB FD-SOI Technology," Proceedings of IEEE International Conference on Design & Technology (ICICDT), 2013',"B. Giraud, J.-P. Noel, A. Grover, O. Thomas, G. Moritz, M. Daud, T. Benoist, Y. Maneglia & D. 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